1. Field of the Invention
This invention relates generally to emitter-coupled logic (ECL) gate arrays and more particularly, it relates to a low voltage current mirror termination circuit for an ECL gate array having output emitter followers so as to reduce power consumption without compromising its operating speed.
2. Description of the Prior Art
A prior art search directed to the subject matter of this application in the U.S. Patent and Trademark Office revealed the following U.S. Pat. Nos.:
______________________________________ 4,439,695 4,651,083 4,528,496 4,704,654 4,565,973 4,733,162 4,587,478 4,760,286 4,628,249 ______________________________________
As is generally well known in the art, an ECL macrocell function is typically formed of a multi-level transistor structure and an output emitter follower, which performs specified logical functions and is based on an identified circuit principle. For example, there is shown in FIG. 1A a conventional two-level ECL macrocell function which performs OR/AND logical operations. The symbolic representation of the OR/AND logical operations of FIG. 1A is illustrated in FIG. 1B. As can be seen, the first level includes a pair of input transistors Qa, Qb and a first reference transistor Qra. An input signal A is applied to the base of the transistor Qa, an input signal B is applied to the base of the transistor Qb, and a first reference voltage VA is applied to the base of the transistor Qra.
The second level includes a pair of input transistors Qc, Qd and a second reference transistor Qrb. An input signal C is connected to the base of the transistor Qc, an input signal D is connected to the base of the transistor Qd, and a second reference voltage VB is connected to the base of the transistor Qrb. A first power supply source GND, which is typically at 0 volts, is connected to the collectors of the input transistors Qa, Qb. A switch current Is is coupled between the common emitters of the transistors Qc, Qd and Qrb and a second power supply source VEE, which is typically at -5.0 volts.
Further, there is provided an output emitter follower transistor Qo whose emitter provides a first output X. A diode is connected between the first output X and a second output Y. An emitter follower reference current source Ief is connected between the second output Y and a separate emitter follower power supply source VEF. The amount of the emitter follower reference current Ief being drawn through the output emitter follower transistor Qo is typically equal to two or three times the value of the switch current Is. Accordingly, the amount of power consumption by an array of ECL macrocell functions similar to FIG. 1A may be significantly reduced by decreasing the voltage of the emitter follower power supply source VEF.
There have been many attempts made in the prior art to lower the voltage of the emitter follower power supply source VEF as shown in FIGS. 2A, 2B and 2C and more fully discussed below in the section entitled "Description of the Preferred Embodiments." However, the circuit arrangement of FIGS. 2A-2C each suffer from certain disadvantages and thus made their performance less than satisfactory.